1. Field of the Invention
The present invention relates to a semiconductor memory device capable of reading at high speed.
2. Description of the Background Art
A semiconductor memory device used mainly in a recent computer, such as a synchronous dynamic random access memory (SDRAM), performs a read operation with a combination of an activate command (ACT command) activating a word line and a read command (RD command) reading a value stored in a sense amplifier. Performing a burst operation outputting data at plural column addresses continuously, SDRAM can outputs data without a pause even if RD commands for the same word line are continuously inputted.
In a case where a read/write operation is performed on a memory cell connected to another word line, however, it is required that after a word line activated currently is deactivated, an objective word line is activated. Since a time is necessary for the operation, read-out data is interrupted somewhere in the course, thereby reducing an effective value of a transfer rate.
In SDRAM, in order to prevent reduction in a transfer rate, a memory region is divided into sections called memory banks each capable of operating independently. In a case where accesses are performed to memory cells at plural row addresses in the same memory bank, however, the effect of division of a memory region into memory banks has not been able to be obtained.
FIG. 21 is a circuit diagram showing a configuration in the neighborhood of a sense amplifier band of a prior art SDRAM.
Referring to FIG. 21, there are placed memory cell arrays MA#00 and MA#11 sharing a sense amplifier band SABX on both sides thereof in which plural sense amplifiers are disposed like a band. Memory cell array MA#00 includes plural memory cells Cell00, Cell10, Cell01 and Cell11 , . . . arranged in a matrix. Each memory cell includes: a capacitor 16 whose one end is fixed to a self-plate potential Vcp at a constant potential; and a transistor 18, connected between a corresponding bit line and the other end of capacitor 16, and having a gate connected to a corresponding word line.
Sense amplifier band SABX includes: a sense amplifier 962; an equalize circuit 922; and a connection circuit 964, all corresponding to a bit line pair BL0 and /BL0. Sense amplifier band SABX further includes: a sense amplifier 963; an equalize circuit 923; and a connection circuit 965, all corresponding to a bit line pair BL1 and /BL1.
Sense amplifier band SABX further includes: an isolation gate 960, becoming conductive in response to activation of a signal BLTG0 to connect bit line pair BL0 and /BL0 to equalize circuit 922 and sense amplifier 962, while isolating sense amplifier 962 and equalize circuit 922 from bit line pair BL0 and /BL0 in response to deactivation of signal BLTG0; and an isolation gate 961, connecting bit line pair BL1 and /BL1 to sense amplifier 963 and equalize circuit 923 in response to activation of signal BLTG0, while isolating sense amplifier 963 and equalize circuit 923 from bit line pair BL1 and /BL1 in response to deactivation of signal BLTG0.
Note that sense amplifier 962 and equalize circuit 922 are also used by bit line pair BL10 and /BL10 included in memory cell array MA#11.
For this reason, sense amplifier band SABX further includes: an isolation gate 966, connecting bit line pair BL10 and /BL10 to sense amplifier 962 and equalize circuit 922 in response to activation of a signal BLTG1, while isolating sense amplifier 962 and equalize circuit 922 from bit line pair BL10 and /BL10 in response to deactivation of signal BLTG1; and an isolation gate 967, connecting bit line pair BL11 and /BL11 to sense amplifier 963 and equalize circuit 923 in response to activation of signal BLTG1, while isolating sense amplifier 963 and equalize circuit 923 from bit line pair BL11 and /BL11 in response to deactivation of signal BLTG1.
In order to reduce a layout area for sense amplifiers, there has been generally well used a shared sense amplifier configuration in which two bit line pairs are disposed on both sides of a sense amplifier.
A sense amplifier is controlled by drive signals S0 and /S0. Since signals S0 and /S0 perform an independent operation in each block, they are differentiated from those for other blocks by attaching each block number thereto. Therefore, for example, a drive signal corresponding to block BLOCK0 is indicated with S0 and a drive signal corresponding to block BLOCK1 is indicated with S1.
Equalize circuits 922 and 923 each include: a transistor being connected to a complementary bit line pair in response to a signal BLEQ and two transistors, being conductive in response to signal BLEQ to couple two bit lines constituting a bit line pair to a potential VBL.
Connection circuits 964 and 965 connect corresponding bit lines to local IO lines LIO and /LIO in response to activation of respective column select lines CSL0 and CSL1.
Data read-out onto local IO lines LIO and /LIO are transmitted onto global IO lines GIO and /GIO through a connection circuit 968 becoming conductive in response to signal IOSW0 and given to an input/output circuit 14.
FIG. 22 is a circuit diagram showing a configuration of a sense amplifier control circuit 1005 generating internal signals mainly used in control of a sense amplifier band of a prior art SDRAM.
Referring to FIG. 22, a control circuit 1002 receives a command CMD and an address ADDRESS, and, in a case where activate command ACT and a precharge command PRE as commands are given externally, when address ADDRESS corresponding to memory block BLOCK0 is inputted, outputs signals ACT0 and PRE0 generated in response to the inputs.
Here, since memory block BLOCK0 is handled as a representative, there will be shown only a configuration associated with signal B0SEL selecting memory block BLCK0 below. For convenience in description, inputted commands are all directed to bank 0 as an object.
Sense amplifier control circuit 1005 includes: a gate circuit 1038 detecting that signal ACT0 is at H level and row addresses RA5 and RA6 are both at L level to activate an output thereof to L level; an inverter 1040 receiving an output of gate circuit 1038; and an SR latch circuit 1042, being set in response to an output of inverter 1040, and being reset in response to signal PRE0. Signal B0SEL indicating selection of memory block BLOCK0 is outputted from the Q output of SR latch circuit 1042.
Sense amplifier control circuit 1005 further includes: a gate circuit 1012 activating an output thereof to L level when signals B0SEL and ACT0 are both at H level and signal RA4 is at L level; an inverter 1014 receiving an output of gate circuit 1012 to invert; a delay circuit 1028 receiving signal PRE0 to delay; and an SR latch circuit 1016, being set in response to an output of delay circuit 1028, and being reset in response to an output of inverter 1014 to output signal BLTG1 from the Q output thereof.
Sense amplifier control circuit 1005 further includes: a NAND circuit 1018 receiving signals RA4, B0SEL and ACT0; an inverter 1020 receiving an output of NAND circuit 1018 to invert; an SR latch circuit 1022, being set in response to an output of delay circuit 1028, and being reset in response to an output of inverter 1020 to output signal BLTG0 from the Q output thereof; and an SR latch circuit 1024, being set in response to an output of delay circuit 1028, and being reset in response to signal ACT0 to output equalize signal BLEQ.
Sense amplifier control circuit 1005 further includes: a delay circuit 1026 receiving signal ACT0; a delay circuit 1030 receiving an output of delay circuit 1026; a NAND circuit 1032 receiving an output of delay circuit 1030 and signal B0SEL; an inverter 1034 receiving an output of NAND circuit 1032 to invert; an SR latch circuit 1036, being set in response to an output of inverter 1034, and being reset in response to an output of delay circuit 1028 to output signal S0 from the Q output thereof; and an SR latch circuit 1044, being set in response to an output of delay circuit 1026, and being reset in response to signal PRE0 to output a signal RAE from the Q output thereof.
Signal RAE is a signal for activating a row decoder 1046 decoding a row address. Row decoder 1046 activates any of word lines WL00 to WL7F in response to activation of signal RAE.
FIG. 23 is an operating waveform diagram for describing operation in a prior art sense amplifier band SABX.
Referring to FIGS. 21 and 23, in an initial state at a time t0, signals BLTG0 and BLTG1 are both at H level and isolation gates 960, 961, 966, and 967 connect senses amplifiers 962 and 963 to corresponding bit lines. At this time, since signal BLEQ is at H level, equalize circuits 922 and 923 are active and bit line pairs are coupled to potential VBL, which is one half of power supply potential VDD.
Drive signals S0, /S0, S1 and /S1 are set to potential VBL. Column select lines CSL0 and CSL1 are both at L level, connection circuits 964 and 965 are both in a non-conductive state to isolate the bit lines and local IO lines LIO from each other.
When, at a time t1, activate command ACT as command CMD is given, signals BLEQ and signal BLTG1 both change from H level to L level. Equalize circuits 922 and 923 are deactivated to cease equalize operations. Isolation gates 966 and 967 isolate bit line pairs BL10 and /BL10, and BL11 and /BL11 from corresponding sense amplifiers.
After a prescribed delay time corresponding to delay circuit 1026 of FIG. 22 elapses, word line WL00 corresponding to a designated row address is activated. Transistors included in memory cells Cell00 and Cell01 become conductive to read out potentials of each memory cell onto corresponding bit lines.
Then, after a delay time corresponding to delay circuit 1030 elapses, drive signals S0 and /SO assume H level and L level, respectively, to activate sense amplifiers. A sense amplifier is activated to amplify a potential difference on a bit line pair.
At a time t2, read command RD and address 00 are inputted externally. Then, column select line CSL0 corresponding to the address is activated to H level to cause connection circuit 964 to be conductive and data amplified by sense amplifier 962 is transmitted to a local IO line pair. In succession, signal IOSW0 is activated to H level to cause connection circuit 968 to be conductive and potentials on a local IO line pair are transmitted to an input/output circuit 14 through a global IO line pair.
When, at a time t3, precharge command PRE is given externally, word line WL00 is deactivated to L level immediately thereafter, and, after a delay time corresponding to delay circuit 1028 of FIG. 22 elapses, signal BLTG1 is set to H level, signal BLEQ is set to H level, signals S0 and /SO are set to an equalize state.
At a time t4, activate command ACT and address 30 are inputted externally. In response to the inputting, word line WL30 is activated to H level and data is read out from a memory cell in a similar manner to the operation at time t1 to perform a sense operation.
At a time t5, write command WRT and address 00 are inputted externally. In response to the inputting, signal IOSW1 and column select line CSL0 are set to H level to write data given from input/output circuit 14 to a memory cell through a global IO line and a local IO line.
At a time t6, precharge command PRE is again inputted externally. In response to the inputting, word line WL30 is deactivated to L level and signals BLTG and BLEQ are set to H level to set a bit line pair to potential VBL. Drive signals S1 and /S1 are both set to potential VBL to enter a standby state.
At a time t8, read command RD and address 01 are inputted externally. In response to the inputting, column select line CSL1 is activated to H level and signal IOSW0 is activated to H level to transfer a potential amplified by a sense amplifier in a similar manner to the case at time t2 to input/output circuit 14 through a local IO line and a global IO line.
In a case where reading or writing is performed on memory cells connected to different word lines in the same bank, a necessity arises for three commands ACT, RD and PRE or ACT, WRT and PRE in each cycle of reading or writing. In this case, since a requirement occurs for a time period three times that in a case where reading is repeated from continuous addresses, an effective data transfer rate is greatly reduced.
Measures to cope with this problem were proposed in the prior art as shown in patent application publications such as Japanese Patent Laying-Open No. 11-250653, No. 11-317072 and No. 2000-137982.
For example, if a latch circuit is provided at a position adjacent to a sense amplifier and data of the sense amplifier is transferred to the latch circuit to be held there, reading of data read out prior to initialization of the sense amplifier can also be performed at high speed from the latch circuit after the initialization of the sense amplifier. However, there remains a demerit of increase in chip area for placement of the latch circuit next to the sense amplifier.
A technique disclosed in Japanese Patent Laying-Open No. 11-250653 adopts a configuration in which plural sense amplifiers are provided to one set of bit line pairs. This technique also has a great demerit of increase in chip area in similar manner, leading to a low possibility of actual usage of products reflecting the techniques.
A technique disclosed in the publication of Japanese Patent Laying-Open No. 11-317072 proposes two architectures in a memory adopting the shared sense amplifier scheme. The first architecture is to activate plural word lines in respective plural blocks by which sense amplifiers are not shared on a basis of one word line per each block. The second architecture is that if a second word line of a second block commonly using the same sense amplifier together with a first block including a first word line selected already is selected successively to the first word line, activation of the second word line and equalization of the sense amplifier are performed in parallel to each other. The first architecture, however, is the same as division of a bank into small units. Any of the first and second architecture has an extremely great number of row addresses to be managed, so a problem occurs that an excessive load is imposed on the memory controller side.
A technique disclosed in the publication of Japanese Patent Laying-Open No. 2000-137982 is an application filed for an improvement memory called as FCRAM having a high speed cycle, wherein since initialization of a sense amplifier is performed during reading, an architecture is required for transferring data of a burst length in parallel to buffers, also resulting in a great demerit of increase in chip area.
It is an object of the present invention to provide a semiconductor memory device having an improved effective data transfer rate in a case where reading and writing are continuously performed on memory cells connected to different word lines in the same bank.
According to an aspect of the present invention, a semiconductor memory device includes: a first memory cell array; a second cell array; a sense amplifier band; and a control circuit.
The first memory cell array includes: a group of plural first memory cells arranged in a matrix; a first bit line pair; and a group of first word lines provided so as to intersect with the first bit line pair. The second memory cell array includes: a group of plural second memory cells arranged in a matrix; a second bit line pair; and a group of second word lines provided so as to intersect with the second bit line pair. The sense amplifier band includes a sense amplifier shared by the first and second bit line pairs. The control circuit controls initialization of the sense amplifier, initialization of the first and second bit line pairs and activation of the groups of first and second word lines. The control circuit, in response to a first command, not only outputs a timing signal changing from an inactive state of one word line of the groups of first and second word lines to an active state thereof, but also cancel initialization of the first and second bit line pairs and initialize the sense amplifier for a prescribed period.
According to another aspect of the present invention, a semiconductor memory device includes: a first memory block; a second block; a switch circuit; and a control circuit.
The first memory block includes: a first memory cell array including a group of plural first memory cells arranged in a matrix, a first bit line pair, and a group of first word lines provided so as to intersect with the first bit line pair; a second memory cell array including a group of plural second memory cells arranged in a matrix, a second bit line pair, and a group of second word lines provided so as to intersect with the second bit line pair; and a first sense amplifier band including a first sense amplifier shared by the first and second bit line pairs.
The second memory block includes: a third memory cell array including a group of plural third memory cells arranged in a matrix, a third bit line pair, and a group of third word lines provided so as to intersect with the third bit line pair; a fourth memory cell array including a group of plural fourth memory cells arranged in a matrix, a fourth bit line pair, and a group of fourth word lines provided so as to intersect with the fourth bit line pair; and a second sense amplifier band including a second sense amplifier shared by the third and fourth bit line pairs.
The switch circuit is provided between the first and second memory blocks and connects the second bit line pair to the third bit line pair. The control circuit controlling the first and second sense amplifiers and the switch circuit to cause data to transfer between the first and second sense amplifiers.
Accordingly, a main advantage of the present invention is that since data read out into a sense amplifier is held till a word line activation instruction is issued, the data held there can be read at high speed prior to activation of a word line.